The context of the invention is a system structure constructed of processes which communicate using messages. Processes are sets of elementary tasks (elementary programs that can be loaded and that can run in the system). A process may be initially created in several processors and executed in these different processors, with specific data to be processed by each processor. The messages allow the communication between the processes. As an example, a requester process sends a specific message to make a request to some server process, which provides, accordingly, information or processing.
As an example, in a communications controller including an intelligent shared memory of the type described in European patent application No. 88480102.8, the Line Interface Modules (LIMs) communicate through the shared memory, and the process performed on data in each specific LIM is an example of a process as referred to in the present application.
Traditional operating systems or control programs provide a set of functions to create queues for holding the messages until they are handled. There are two main operations performed on these queues, namely enqueing messages and dequeing messages. Different tasks may work on the same queues. The set of distributed processes which work on a same queue of data messages is known as a process group.
The scheduler is the coordinator of the different process requests. A scheduler performs the function of an arbitrator within a processor or a group of processors, depending on whether a decentralized or a centralized architecture is considered. In known centralized scheduling mechanisms, the scheduler is aware of all the requests posted by tasks within the process group. Therefore, in the case of numerous tasks which are distributed in several processors (it is the case when the software path lengths within a single processor are too high), the central scheduler constitutes a bottleneck.
Moreover, the central scheduling mechanism implies processor to processor communications to ask for messages and to receive messages. Thus, if the processor containing the central scheduler comes to fail, then all the processes belonging to the related process group will also fail.
Consequently, the known central scheduling mechanism appears not to be tolerant to component failures, even single component failures.
For an example of centralized scheduling mechanism, it can be referred to European patent No. 0 230 721, showing a single centralizd scheduler located in a Host computer.
In the contrary, in a decentralized scheduling mechanism, there are as many schedulers involved as there are processors in the process group.
However, in known decentralized scheduling mechanisms, the decentralized schedulers are dependant on both decentralized processes and decentralized data to be used by said processes. This cannot be conciliated with a shared memory environment, wherein the available memory space is shared by several loosely coupled processors.
As a matter of example, an approach of a decentralized scheduling mechanism is described in U.S. Pat. No. 4,387,427 and in European patents 0183817 and 0230721.
While U.S. Pat. No. 4,387,427 discloses a process dispatcher which involves dual-purpose queuing of both messages of a process and the processes themselves, the remaining above mentioned documents disclose time-shared source processors which choose target processors in a deterministic way.
In summary, the scheduling mechanisms as taught by the prior art are, if not centralized, decentralized but incapable of working with fully shared tasks and independant schedulers.